This invention relates to digital counters, and more particularly, to digital counters used to derive from a system clock one or more subsystem clocks.
Digital counters are a common component of digital systems. A typical digital system includes a system clock, and on each cycle of the system clock the counter will count. The count can be either up (e.g., from 0 to M, where M is an integer) or down (e.g., from M to 0), which ever is most convenient to implement. The counter could be programmable (e.g., M is programmable), or the counter could be hardwired (e.g., M is a single, fixed value, determined by how the counter is constructed). The counter has many applications, including timing (e.g., event timing or delay loop), and dividing down the system clock to a slowing frequency.
In general, the design of a clock is relatively straight forward. Clock design becomes tricky, however, as the desired clock frequency increases. At clock frequencies much above 10 MHZ, careful layout is needed to minimize EMI, clock skew, and other problems. At clock speeds approaching 100 MHz, these problems are even more severe, with connections between the clock and other circuit elements more resembling wave guides than simple wires.
One approach to reducing the required clock rate is to use a multiphase clock. In a multiphase clock, each clock phase operates at the same rate as the other clock phases, but out of phase with the other clock phases. With proper design, successive phases of a multiphase clock can be used to clock successive stages of a sequential logic circuit, thereby creating an effective clock rate of (no. of phases) * (clock frequency). For example, a simple two phase system clock would consist of a "clock" and its inverse, clock. Clock would be 180 degrees out of phase with clock. In a particular system, the effective clock rate of a system could be almost doubled by judicious allocation of clock and clock to clocking various logic elements. For example, a Master-Slave Flip Flop could be clocked by clocking the Master stage with clock, and clocking the Slave stage with clock.
Some digital systems require multiple clocks, operating at different clock rates or frequencies. Often the most practical approach to generating these clocks is to build a single systems clock that runs at a high enough frequency that all other clocks can be obtained by simply dividing (i.e., counting) the systems clock. A simple example is a digital system having three subsystems, one requiring a 2 MHz clock, one a 3 MHz clock, and the third a 4 MHz clock. To minimize the frequency of the systems clock, the choice of systems clock should be the least common multiple of these three subsystems clocks, or 12 MHz. The 2, 3 and 4 MHz subsystem clocks could be provided by dividing the 12 MHz systems clock by divisors of 6, 4 and 3, respectively.
While this least common multiple approach is generally adequate, the required system clock can be prohibitively high. The multiphase system clock can be divided down to produce multiphase slower clocks. In particular, each phase of a multiphase system clock can be divided down to a new clock signal, care being taken to maintain the phase relationships in tact. Alternatively, a single phase of a system clock signal can be divided down to create the new slower clock, and this slower clock then can be used to generate a multiphase clock signal at the slower clock rate.
For multiphase clocks (system or otherwise), the general case is an L-phase clock (L is an integer), with clock phases being spaced symetrically 360/L degrees apart in phase. This approach achieves a maximum possible effective clock of L times the system clock. A popular multiphase clock scheme is the quadrature clock (e.g., four phases, successive phaseses being 90 degrees apart).
Of course, there are practical limits to the number of phases into which a given clock can be split. Moreover, achieving this maximum effective clock rate requires that sequential logic elements are clocked by successive phases of the clock.
The combined multiphase, system clock approach has generally proven adequate. However, the divided subsystem clocks are limited to counting down the subsystem clock, which is 1/(Number of Phases, L) the frequency of the effective system clock. There is therefore a need for a clock divider that makes full use of the multiphase system clock to allow integer divisors of the effective system clock, rather than just integer divisors of the system clock.
More generally, there is a need for a combined clock and counter, with the clock having L phases, and the counter is capable of counting at a frequency scaled by L. There is a further need for the counter to be programmable "on the fly," and to generate an output signal that has a substantially even mark-space ration (i.e., substantially a 50% duty cycle).